In typical CMOS circuitry, semiconductor devices with multiple fingers are utilized and distributed over a wide area of a chip for various purposes. The multifinger semiconductor devices can also be considered multiple parallel devices with a common control component, such as a gate of a transistor or a thyristor. A typical example is an electrostatic discharge (ESD) protection circuit that requires placement of multiple fingers of a MOSFET in a parallel connection that is spread over a chip. In this case, distribution of multiple fingers across the chip area is not only advantageous but necessary to provide maximum protection against a potential electrostatic discharge event that might happen anywhere on the chips. By connecting the sources and drains of the individual fingers in a parallel connection to form a large multifinger gate-grounded NMOSFET (GGNMOSFET), the ESD device can handle a higher amount of electrostatic charge than any individual finger.
In an ESD event, it is preferred that all the fingers of a multifinger ESD protection MOSFET turn on to maximize the charge handling capacity of the ESD circuit since the magnitude of voltage spike on the circuit is inversely proportional to the amount of current the multifinger ESD protection MOSFET can pass. However, the multiple fingers of the ESD protection MOSFET typically do not turn on simultaneously due to differences in circuit parameters among the multiple fingers. To make matters worse, once a finger turns on, the voltage on the drain, which is shared by all the fingers in the multifinger MOSFET, snaps back to a lower value, preventing a turn on of the remaining fingers. In this case, the amount of current the ESD protection MOSFET can pass is limited to the current that the one turned-on finger can pass.
FIG. 1 shows a semiconductor chip with an ESD protection MOSFET circuit provided with multiple fingers that are distributed over the chip area. One finger 10 of the ESD protection MOSFET is circled with references made to the drain 12, gate 14, and source 18. The substrate ring contact 19, or the guard ring is shown in FIG. 1 as well. The source of each finger 10 of the ESD protection MOSFET electrically contacts the substrate ring contact 19 to ground the ESD protection circuit.
FIG. 2A shows an electrical circuit comprising a finger 20 of an ESD protection NMOSFET along with an I/O pad 21. The gates of the fingers are tied together and connected to the ground, forming a gate-grounded NMOSFET (GGNMOSFET) configuration. The finger 20 comprises a drain 22, a gate 24, a source 28, a parasitic npn bipolar transistor, and a parasitic resistor 27. Also, a parasitic impact ionization current source 23 is shown between the body 26 and the drain 22 of the finger 20.
The parasitic npn bipolar transistor and the parasitic resistor 27 result from the physical structure of the finger 20 of the ESD protection NMOSFET. In a typical CMOS circuit, NFETs are built in the P-substrate with an n-doped source 28 and an n-doped drain 22. The source 28, the body 26, and the drain 22 of an NFET therefore form a parasitic npn bipolar transistor, with the source 28 being the emitter, the body 26 being the base, and the drain 22 being the collector. Since the semiconductor material forming the source 28 and the body 26 has a finite resistance, there is a parasitic resistance between the source 28 and the body 26 of each finger. Also, since the source 28 is tied to a substrate ring contact 19 that is placed around the periphery of the chip area, there is a finite resistance between the source 28 and the substrate ring contact (not shown explicitly in FIG. 2A). The parasitic resistance 27 reflects the two parasitic resistances mentioned above and has a resistance value for the path from the body 26 to the substrate ring contact. The circuit in FIG. 2 therefore reflects the parasitic components of a physical finger 10 of the ESD protection NMOSFET circuit shown in FIG. 1.
The impact ionization source 23 simulates the parasitic impact ionization current in the reversed biased junction between the body 26 and the drain 22 of one finger of the NMOSFET. This occurs naturally since the drain 22 is N-doped and the body 26 is in a P-doped substrate while a more positive voltage is applied to the drain 22 relative to the body 26 and thus forming a reversed biased diode. This current can be modeled as an exponential function of the drain-to-body voltage.
Examination of FIGS. 1 and 2A shows the source of the differences in the circuit parameters among the various fingers 10 of an ESD protection NMOSFET. Even if the non-parasitic characteristics of each finger 10 of the ESD protection NMOSFET is matched, the parasitic components are different. Specifically, the resistance of the parasitic resistor 27, or the “substrate resistance,” heavily depends on the location of the finger since it includes the resistance between the source 28 and the substrate ring contact 19. A finger nearer to the substrate ring contact 19 has a lower parasitic resistance than another finger that is farther away from the substrate ring contact. However, multiple fingers are generally required to handle the large amount of current during an ESD event. To turn on the multiple fingers of an ESD protection NMOSFET during an ESD event at the same time, the trigger voltage, or the voltage at the drain 22 of a finger 20 above which the finger 20 turns on, needs to be matched.
A study demonstrating a nonuniform turn-on of a multi-finger ESD protection MOSFET is shown in Lee et al., “The Dynamic Current Distribution of a Multi-fingered GGNMOS under High Current Stress and HBM ESD Events,” IEEE 44th IRPS, 2006, pp. 629-630. Lee et al. observed that during the initial transient of an ESD discharge, the current distribution is non-uniform in a GGNMOSFET according to the measurements performed on a nanosecond time scale.
A first prior art solution to this problem is to add drain ballasting resistance to individual fingers of an ESD protection MOSFET. However, this approach requires a large area of semiconductor substrate for such drain ballasting resistors. Furthermore, the addition of drain ballasting resistors adds large on-resistance in the circuit, effectively reducing the current capacity of the ESD protection MOSFET and thus, requiring a large clamping voltage.
A second prior art solution disclosed in Duvvury, “Substrate Pump NMOS for ESD Protection Applications,” Proc. EOS/ESD Symp, 2000, 2000, pp. 1A.2.1-11, utilizes a substrate pump to achieve a uniform triggering voltage for a multi-finger NMOS ESD circuit. A third prior art solution disclosed in Mergens et al., “Multi-finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling,” Proc. EOS/ESD Symp, 2001, pp. 1-11, uses a domino-type NMOS multi-finger transistor wherein the source of a finger is connected to the gate of an adjacent finger in a cascade configuration.
While the prior art solutions tend to equalize the trigger voltages across the multiple fingers, they also tend to introduce additional resistance to the circuit. Additionally, the semiconductor area used for the prior art solutions are significant. Also, the ability to tune the trigger voltage so that a circuit would turn on at a predetermined bias voltage is also desired.
While the discussions above is limited to multi-fingered GGNMOSFETs, there is also need to control the turn-on of other multi-fingered devices such as general NMOSFETs, general PMOSFETs, and thyristors, especially when the multiple fingers of such devices are spread over a large area of a chip.
FIG. 2B shows an electrical circuit comprising a finger 20B of a PMOSFET with an I/O pad 21. The finger 20B comprises a drain 22B, a gate 24B, a source 28B, a body 26B, which is also the base of a parasitic pnp bipolar transistor, and a parasitic resistor 27B. An impact ionization current source 23 is present between the body 26B and the drain 22 B in this circuit.
FIG. 2C shows an electrical circuit comprising a finger 20C of a multi-finger thyristor with an I/O pad 21. A thyristor has a pnpn semiconductor structure. In a typical thyristor, the outer p-doped region is the anode and is connected to a positive power supply, the outer n-doped region is the cathode and is connected to a negative power supply, and the inner p-doped region is the gate and is connected to a control input. The finger 20C comprises an anode 22C, a gate 26C, a cathode 28C, and a parasitic resistor 27C. Also, an impact ionization current source 23C is a built-in component of the thyristor between the gate 26C and the cathode 28C of the finger 20C since the thyristor contains a reverse biased PN junction between the anode 22C and the gate 26C. The multiple fingers of a thyristor need to turn on at the same time to fully utilize the current capacity of the thyristor. An alternate configuration wherein the gate is connected to the inner n-doped region and corresponding alteration of circuit is herein contemplated.
In FIG. 3, an exemplary prior art ESD protection NMOSFET circuit is shown, wherein five fingers (30A-30E) are connected in a parallel connection. One end of the parallel connection of five fingers which connect the drain of each finger is connected to an I/O pad 31, which is connected to a positive power supply. The other end of the parallel connection of five fingers which connect the source of each finger is connected to a substrate ring contact 39, which is connected to ground.
Each of the fingers (30A-30G) has a parasitic bipolar transistor wherein the base (36A-36E) is the body of each finger, a parasitic injection source (33A-33E), and a parasitic resistor (37A-37E). If a design layout for each finger (30A-30E) is the same, each finger (30A-30G) has substantially the same amount of parasitic injection current. However, due to the differences in the physical resistive paths between the body (36A-36B) of each finger and the substrate ring contact 39, the resistance values of the parasitic resistors (37A-37E) are different from finger to finger. This results in variations in the trigger voltage, i.e., the voltage at the drain above which each finger to turn on. As described above, non-uniform trigger voltages across the fingers can lead to a condition wherein not all of the fingers are turned on during an ESD event.
The above problem is generic across semiconductor devices of which the trigger voltage, or the turn-on voltage, is dependent on the value of a parasitic resistance of the device. Other than multi-finger ESD protection NMOSFETs, multi-finger NMOSFETs in general, multi-finger PMOSFETs in general, and multi-finger thyristors in general have a parasitic resistance dependent trigger voltages for their fingers, and as a consequence, not all of the fingers may turn on when the device needs to be turned on.
Therefore, there exists a need for a structure and circuit technique for achieving a uniform turn-on of multi-fingered semiconductor devices without adding resistive components or with a minimal addition of resistive components.
There also exists a need for a structure and circuit technique for achieving a uniform turn-on of multi-fingered semiconductor devices with a minimal additional area for the added circuit components.
Furthermore, there exists a need for a structure and circuit technique for tuning a turn-on voltage, or a trigger voltage, of multi-fingered semiconductor devices.